As is known in the art, the performance and complexity of semiconductor structures and devices has drastically increased over the past several decades and will likely continue to increase. Additionally, the circuit density of semiconductor structures and devices has increased, resulting in more circuitry in a given space. By employing clever techniques and new materials, however, the semiconductor industry has managed to overcome some of the physical barriers that had been predicted to occur (e.g., via Moore's Law), allowing for the continued progression (and miniaturization) of semiconductor structures and devices. One such technique that has generated interest in recent times is the stacking (e.g., vertical stacking) and bonding (e.g., electrical coupling) of individual semiconductor structures to form multi-layer semiconductor structures, which are commonly referred to as three-dimensional (3-D) integrated circuits (ICs). One such multi-layer semiconductor structure is described in U.S. Pat. No. 7,067,909 entitled “Multi-layer integrated semiconductor structure having an electrical shielding portion,” which is assigned to the assignee of the present disclosure and incorporated herein by reference in its entirety.
In fabricating multi-layer semiconductor structures, such as that which is described in the above-referenced U.S. Pat. No. 7,067,909, for example, the individual semiconductor structures forming the multi-layer semiconductor structures are typically positioned and aligned with respect to each other and then placed in a contact relationship prior to bonding to ensure precise alignment of the semiconductor structures when bonded and stacked. The individual semiconductor structures are then bonded form the multi-layer semiconductor structure. The ability to precisely position, align and bond these individual semiconductor structures can have a significant impact on achievable circuit density of the multi-layer semiconductor structure. For example, the accuracy with which with individual semiconductor structures can be aligned determines, at least in part, the number of semiconductor structures which may be stacked to form a multi-layer semiconductor structure.